verilog 代写 综合 Xilinx Matrix Multiplier Assignment

EE 201A Final Project

Winter 2015 DUE: Before March 22nd 23:59

Problem:

Given two 4×4 matrixes A and B, where matrix A can be any integer value

and matrix B is a constant matrix as Fig. 1 shows, design a matrix multiplier

module that performs matrix multiplication of A x B:



AAAA

14131211



AAAA

24232221

AAAA

34333231

AAAA



44434241





4/138/11





28/32/34/3



315/752/1

4/34/1123/1401





Figure 1. A x B

Fig. 2 shows the block diagram of the matrix multiplication, where both

Matrix A and B stored and implemented by BRAMs in the FPGA.

Matrix A

BRAM

Matrix

multiplier

Const.

Matrix B

BRAM

Figure 2.

The BRAM can be generated using Xilinx core generator. More details

about how to generate BRAM and initialize its content, please check

http://youtu.be/RwYjeT8Nf88 . For verification of the matrix multiplier,

following is an example of the BRAM initialization file for matrix A:

memory_initialization_radix = 10 ;