Single Cycle versus Pipeline
In a single-cycle design, every instruction takes exactly one cycle. In other words, the single-cycle design
must allow the slowest instruction. While in pipelining, the datapath is broken into separate stages in-
dependant from each other, named IF (Instruction Fetch) , ID (Instruction Decode), EXE (Execution),
MEM (Memory) and WB (Write Back) in RISC-V. All the pipeline stages take a single clock cycle. As
a result, every instruction in RISC-V datapath takes exactly ve cycles to be executed. According to the
following gure, pipeline registers are located between every two stage. All the gures in this document
extracted from [1].
We can pipeline the tasks as long as we have separate resources for each stage. Pipelining improves
performance by increasing the instruction throughput. The idea behind pipelining is to keep all the stages
busy at all the times. As an example, when an instruction is using the ALU, the register le and the
instruction memory are used by the other instructions. Every instruction seems to have its own datapath.
All instructions advance during each cycle from one pipeline register to the next. In this case, all the required
information of an instruction such as control signals and registers need to be stored in pipeline registers.
Therefore, the instruction is able to restore all the required information for the next pipeline stage. According 

to the following gure, all the datapath information as long as control outputs generated by Controller are
stored in pipeline registers for every instruction.

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