1. Write a structural Verilog code to generate a 2-bit subtractor. The circuit has two 2-bit inputs A and B and outputs S-sum (2-bits) and B-borrow. Write a test bench simulating all possible input combinations and verify your design checking proper output values and delays. To get the gate-level design of the circuit, create (and show in the write-up) the truth table, and then simplify them. (Use Karnaugh maps). Note that you should assume 2s complements for negative numbers.

2. Using the truth table, create a set of user-defined primitives to accomplish the same 2-bit subtractor.

3. Design an 8-to-1 MUX in Verilog. Each input to the MUX is 16-bit in width. You have to write two different modules implementing a MUX:

1) Using a CASE statement and

2) Using IF-ELSE statements.

Verify each module by writing a test bench and simulating selection of each input line.

4. Write and simulate/test a behavi