MIPS 处理器 数据通路设计 verilog代写

EECE 3324
Computer Architecture and Organization
Final Project
MIPS Architecture Implementation
Due on Apr. 14th (M) 11:59pm
Basic project: single-cycle MIPS architecture implementation (worth 25% of the total course points)
1. Overview
For the EECE3324 project, you will implement the standard single-cycle MIPS architecture in Verilog. You are given a memory Verilog file which contains both text (program instructions) and data, you should write a processor Verilog file which contains all the modules for the processor datapath and controller. The processor module interacts with the memory module. You should write your own testbench file to simulate the processor and memory. Finally, you should calculate the CPI of the provided program from the Verilog simulator.
I recommend using Modelsim as the HDL simulator. Instruction file on Modelsim installation and usage have been posted on BB. You can also use others, like ISE simulator, vcs, etc., if you are familiar with them. However, you have to let the TA and me

histogram equalization verilog代写

ECE 464/520: Project Technical Requirements
You are to produce a Histogram Equalization Unit for image processing. A general description of what a histogram equalization unit does can be found on Wilkipedia amongst other sources,
You will be processing a series of small (640 x 480 pixel ) images. The images will contain 32-bit unsigned pixels representing gray scale images. A basic description of the algorithm is found below (this is extracted from a requirements document in one of our research projects.
Change (Feb 6, 2014). The data supplied to you actually has a dynamic range of only 8 bits per pixel. SO that you can all take advantage of this, you only need to produce a histogram where the value of each pixel is sorted into L=28 buckets, not 216 buckets.


You have to design a unit that maximizes the number of images that can be processed per unit area. You thus need to report how long (in seconds) it takes to process an image, and what is the cel

FIFO设计 verilog代写




FIFO(First In First Out)——是一种可以实现数据先入先出的存储器件。FIFO就像一个单向管道,数据只能按固定的方向从管道一头进来,再按相同的顺序从管道另一头出去,最先进来的数据必定是最先出去。FIFO被普遍用作数据缓冲器。




解释与说明:上图中最大的矩形框所包围的内部部分为所设计的同步FIFO,由FIFO主控体和RAM构成。FIFO主控体接收来自外部的读写控制信号(read_n,write_n)、复位信号(reset_n)和时钟信号(clock),并在时钟上升沿到来时根据从RAM返回的counter信号进行读写控制判断以及读写指针的计算,并将所得结果以mwrite_n,mread_n,wr_pointer ,rd_pointer信号的形式传递给RAM进行相应的读写操作。其中counter信号代表RAM体内已存储未读数据的数据个数。整个同步FIFO包括八条外部数据信号线(包括总线)和五条内部数据信号线。





cache设计 verilog代写

In this assignment, you will design a generic memory block and use it to perform various tasks.


Part 1: Memory/cache design.

A physical cache block is made up of memory cells which are associated in rows and columns. Each row corresponds to a cache-line, which may contain any size of data. These lines are then stacked in column form. In general, each cache line consists of 3 major parts, the ID tag, the data, and the state (or status) of each line. The state bits will be ignored for this assignment (just use ID tag and data).

When a request comes in for a line, the cache lines are searched concurrently to determine if a line matches the requested ID tag. If the tag matches, then the bits in the data portion of the cache line are sent out of the system. (Note: this assignment is a scaled down version of a traditional fully-associative cache, not including any sense amplifiers and other support circuitry).

Your job is to design such a cache, with a compile-time vari