• Simulate the two modules for functional correctness with the testbenches provided. Ensure that the generated result matches golden result provided.
• Perform synthesis checks with OpenRAM memory modules.

Design Description:

To build the hardware, for the FPGA implentation you are provided a simple dual port memory module, mem. v, which you can use to instantiate memory blocks accordingly. For ASICs, OpenRAM is used to generate SRAM blocks.
A high-level picture of the memory structure is shown below. You have to design s2mm. sv and mm2s. sv blocks.

OpenRAM: SRAM Blocks
The lab manual on OpenRAM provides details of how OpenRAM is used and configured to generate SRAM macros. The description here details how OpenRAM is used in this lab.
The configuration file config_sram_lr _lw. py is used to configure the SRAM macros needed for Lab4. In this lab memories are instantiated in s2mm. sv and mm2s. sv. The details of these modules will be expanded in the next two sections, the memory requirements are summarized below.
Memory in s2mm. sv has the following requirements:

• Port : 1 Read 1 Write
• Width : 32
• Depth : Atleast M*M/N

Memory in mm2s. sv has the following requirements:

• Port : 1 Read 1 Write
• Width : D_W*2
• Depth : Atleast M*M/N

For each module and combination of paremeters M, N and o_w, different RAMs need to be generated.
Note: OpenRAM and the reference memory block given to you in mem. v have similar timings (NOT exact). You can use this in your design.
Stream to Memory-Mapped s2nwn.sv:
The systolic core previously designed in Lab 3 requires the input matrices A and B are streamed to the system one element per cycle with suitable phase offsets for different rows and columns. When M>N, we have to reuse data as multiple sub-matrix multiplications are needed. Consequently, some form of memory structure is needed for the purpose of holding the matrix elements before they are presented to the NxN. As a result, each memory block will be holding M*M/N matrix elements.

Writing Mechanism:
The s2mm.sv module has several inputs, two of which are s_axis_s2mm_tdata and s_axis_s2mm_tvalid, which represent streamed data and valid signals, respectively. Since only one data port and one valid port are available to us, the data/valids must be streamed serially across the 2*N memory blocks. For high-frequency operation, your design should pipeline the data/valids across the 2*N memory blocks through a set of 2*N pipeline stages (or shift registers). You must also generate write addresses and memory enable signals internally based on the system inputs/outputs. The mechanism for writing the 2*N memories is sequential such that the i th set of streamed M*M/N matrix elements is written to the ith memory block, so that eventually 2*M*M values are written in total. Note that all data that is written to memory should be valid. You can assume that s_axis_s2mm_tready signal is set to 1 which permits the host CPU to send you data continuously without interruption if possible. The inputs s_axis_s2mm_tkeep and the s_axis_s2mm_tlast signals can be ignored for this design.